1. Field of the Invention
The present invention relates to a semiconductor device having an ESD (Electro Static Discharge) protecting element. The invention can be applied to a semiconductor device which needs a constant resistance in a limited area, and can be suitably applied to, particularly, a case where the ballast resistance of the ESD protecting element is provided.
2. Description of The Related Art
With the recent enhancement of the functions and the performance of semiconductor devices, there is a demand for multi-pin semiconductor devices which have over several thousand I/O (Input/Output) pins. Accordingly, the area of a single I/O block considerably influences the downsizing and cost reduction of the overall semiconductor device. Elements which have a large ratio of occupying the area of the I/O block are an ESD protecting element and a driver element of high drive power. A multi-finger type protecting element which has a plurality of MOS (Metal Oxide Semiconductor) transistors (fingers) with a gate width of several ten micrometers connected in parallel is used as the ESD protecting element.
FIG. 1 is a graph showing the operational characteristic of an ESD protecting element with a voltage to be applied to the ESD protecting element taken on the horizontal axis and a current flowing through the ESD protecting element taken on the vertical axis. FIG. 1 is an exemplary diagram so that the sizes of the voltage and the current should not necessarily match with actual measurements.
As shown in FIG. 1, there are two types of voltages which are actually applied to an ESD protecting element, a voltage in the direction where snap-back occurs and a voltage in the direction where snap-back does not occur. The voltage in the direction where snap-back occurs is a voltage in the direction where the amount of the flowing current can be changed by controlling the gate voltage, i.e., a voltage in the direction in which the voltage is applied at the time of operating the ESD protecting element. In case of an NMOS transistor, for example, it is a voltage in the direction where the drain becomes a positive potential and the source becomes a negative potential. In case of a PMOS transistor, it is a voltage in the direction where the source becomes a positive potential and the drain becomes a negative potential. The voltage in the direction where snap-back does not occur is a voltage which is applied in the opposite direction to the voltage in the direction where snap-back occurs.
For the object of descriptive simplicity, in the following description, the voltage in the direction where snap-back occurs will be called a “positive ESD voltage” and the current flowing in this direction will be called a “positive ESD current”, while the voltage in the direction where snap-back does not occur will be called a “negative ESD voltage” and the current flowing in this direction will be called a “negative ESD current”. As how snap-back occurs normally matters in the discussions on an ESD protecting element, the positive ESD voltage is often discussed. In the present specification, the ESD voltage is a positive ESD voltage and the ESD current is a positive ESD current unless the positive or negative polarity is specifically mentioned.
As indicated by a solid line 101 in FIG. 1, the current monotonously increases with respect to the voltage within a range where the voltage to be applied to the ESD protecting element is low, but when the voltage exceeds a given threshold, a parasitic bipolar transistor whose drain region, channel region and source region respectively become the collector, the base and the emitter is formed in the MOS transistor. As the parasitic bipolar transistor operates, the ESD protecting element snaps back to reduce the resistance, so that a large current flows into the ESD protecting element. If the ESD protecting element is comprised of an MOS transistor alone which is formed by a salicide process (self-align silicide process), the operational characteristic becomes as indicated by a broken line 102.
In this case, however, a problem would arise. As shown in FIG. 1, provided that the maximum allowable current per one finger in multiple fingers is X, when the characteristic of each finger is as indicated by the broken line 102, the first finger that has snapped back is broken by the current that flows in this finger. In this respect, a ballast resistance is added to the drain of the MOS transistor to set the characteristic of each finger to the one shown by a broken line 103. That is, a breakdown voltage VB1 over which a finger is broken is set higher than a snap-back start voltage VSP1. With the design, before the first finger that has snapped back is broken, the other fingers sequentially snap back, thus letting the ESD current to flow. Therefore, the current does not concentrate on one finger so that the overall ESD protecting element would not be broken.
As well known, with the scale of integration of semiconductor elements becoming higher, silicide is formed at the top surfaces of the gate electrode and the source region and the drain region. As the silicide has a low surface resistance, the operational characteristic of the ESD protecting element becomes as indicated by the broken line 102 in FIG. 1, which would raise a problem in view of protection against ESD.
Japanese Patent No. 2773221 discloses a technique of setting a region where no silicide is formed or a silicide blocking region in the drain region, thereby increasing the resistance of the drain region. FIG. 2 is a plan view showing a conventional ESD protecting element described in Japanese Patent No. 2773221. As shown in FIG. 2, this conventional ESD protecting element, 111, has a source region 112 and a drain region 113 provided at the top surface of a semiconductor substrate. A gate 114 is provided on a region between the source region 112 and the drain region 113. A silicide blocking region 115 is provided at the top surface of the drain region 113. A Ti silicide 116 is formed in the other regions of the top surfaces of the source region 112, the gate 114 and the drain region 113 than the silicide blocking region 115. This increases the resistance of the drain region, and adds a ballast resistance.
Japanese Patent Laid-Open Publication No. 2001-284583 discloses a technique of adding a ballast resistance by using a well resistor. That is, a deep drain diffusion region is formed at the top surface of the silicon substrate. Then, a trench isolation layer is formed in such a way as to separate the deep drain diffusion region and the salicide formed at the top surface thereof into two parts, one on the channel side and the other on the contact side. At this time, the trench isolation layer is formed shallower than the drain diffusion region, and a current path is formed in the drain diffusion region in such a way as to go around the lower portion of the trench isolation layer. Japanese Patent Laid-Open Publication No. 2001-284583 describes that the design can add a ballast resistance to the current path of the ESD current and the snap-back voltage can be controlled by controlling the size and the position of the trench isolation layer.
A literature ‘Koen G. Verhaege and Christian C. Russ, “Wafer Cost Reduction through Design of High Performance Fully silicided ESD Devices”, EOS/ESD Symposium 2000, p. 18–28’ discloses a technique of connecting a resistor of polysilicon to the drain region. FIG. 3 is a cross-sectional view showing the conventional ESD protecting element. As shown in FIG. 3, in the conventional ESD protecting element, 120, a P well 133 is formed at the top surface of a P type silicon substrate 121, and a source region 122 which is an n+ type diffusion region, a gate 123 and a drain region 124 which is an n+ type diffusion region are formed at the top surface of the P well 133, thereby forming an MOS transistor 125. The drain region 124 is connected to one end of a resistor 129 via a contact 126, a wire 127 and a contact 128. The other end of the resistor 129 is connected to a pad 131 via a contact 130. The resistor 129 is formed on a device isolation layer 132 formed at the top surface of the silicon substrate 121, and is insulated from the silicon substrate 121 by the device isolation layer 132. A p+ type diffusion region 134 is formed at the top surface of the P well 133, and is applied with the ground potential. The literature describes that a ballast resistance can be added by the resistor 129 of polysilicon.
The prior arts however have the following problems. First, according to the technique described in Japanese Patent No. 2773221 which forms a ballast resistor with a silicide blocking region, the sheet resistance of the silicide blocking region is 200Ω/□ or so, so that when the total gate width of the ESD protecting element is 600 μm, the width of the silicide blocking region should be set to 2 μm in order to form a ballast resistor of 0.6Ω. To acquire a large ballast resistance required, therefore, the source and drain gap becomes larger to, for example, 3 to 4 μm or so. The technique requires a special step of forming the silicide blocking region.
According to the technique described in Japanese Patent Laid-Open Publication No. 2001-284583 which forms a ballast resistor with the resistance of a drain diffusion region, it is necessary to form the drain diffusion region deep. A thick resist is therefore needed at the time of forming the drain diffusion region deep. This makes it difficult to control the horizontal shape precisely and stands in the way of designing the element compact.
The technique disclosed in the literature by Koen G. Verhaege and Christian C. Russ which forms a ballast resistor with a resistor of polysilicon has a problem that when a negative ESD current is supplied to the pad 131, a resistance is added to the current path of the ESD current as shown in FIG. 3. In the ESD protecting element 120, a PN diode is formed between the P type silicon substrate 121 and the n+ type drain region 124. When a negative ESD current is supplied to the pad 131, the current flows in the path of the P well 133—drain region 124—contact 126—wire 127—contact 128—resistor 129—contact 130—pad 131, as indicated by arrows in FIG. 3, a resistance provided by the resistor 129 is added to the current path. When a negative ESD current is supplied to the pad 131, however, the ESD protecting element does not snap back, no ballast resistor is required, and the ballast resistor, if present, would reduce the protection performance. In other words, the conventional ESD protecting element has a low protection performance against a negative ESD current.